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[ak7722] ms1328-e-00-pb - 1 - 2011/09 general description the ak7722 is a digital signal processor with an integr ated 4ch 24bit dac, a stereo adc with input selector and a 2ch input adc. the integrated 4ch dac, the 2ch adc with input selector and the other 2ch adc feature high performance achievi ng 108db, 96db and 95db, respectively . the integrated src has three input selector enabling the dsp to operate in ma ster mode with digital inputs. the audio dsp has 1536step/fs (at 48khz sampling) parallel arithmetic operation performance and the 5k-word delay ram allows surround processing and time alignment adjus ting. as the ak7722 is a ram based dsp, it is programmable for various user requirements. it is housed in an 80pin lqfp package. features [dsp block] - word length: 24bit (coefficient ram & data ram: f24 floating point) - processing speed: 13.6 ns (1536step/fs; fs = 48khz) - multiplication: 20 x 24 44-bit double precision arithmetic available - divider 20 / 20 20bit - alu: 48bit arithmetic operation (overflow margin 4bit) 20bit floating point arithmetic and logic operation - program ram: 3072 x 36bit - coefficient ram: 2048 x 24bit (f24 floating point) - data ram: 2048 x 24-bit (f24 floating point) - offset register: 64 x 13bit - delay ram1: 3072 x 24-bit - delay ram2: 2048 x 24-bit - sampling rate: fs= 7.35k ~ 48khz - master clock: 1536fs (generated from 32fs, 48fs, 64fs, 128f s, 256fs, 384fs by internal pll) - master/slave operation [adc1 block] - stereo with 6 inputs selector - dr, s/n: 96db (fs = 48khz , when differential input) - s/(n+d): 90db (fs = 48khz) - differential & single-ended inputs - digital hpf (fc=1hz) - 6 analog inputs selector (2 differential, 4 single-ended) - digital volume control (24db ~ -103db, 0.5db step, mute) [adc2 block] - dr, s/n: 95db (fs = 48khz) - single-ended inputs - digital volume control (24db ~ -103db, 0.5db step, mute) [src block] - 3 pair of stereo 1 stereo pair selector - 2ch x 1 system - supporting frequency: fin = 7.35khz ~ 96khz fout = 7.35khz ~ 48khz (fso/fsi = 0.167~ 6.0) 24bit 4ch adc + 24bit 4ch dac with audio dsp ak7722
[ak7722] ms1328-e-00-pb - 2 - 2011/09 [guidance src block] (gsrc) - 1 channel (24bit) up-converter for voice guidance - supporting frequency: fin = 7.35khz ~ 12khz fout = 44.1khz or 48khz [dac block] - 4ch (2 stereos) - 24bit 128 x over-sampling advanced multi-bit (fs=8khz~48khz) - dr, s/n: 108db (differential output) - s/(n+d): 90db - digital volume control (12db ~ -115db, 0.5db step, mute) [digital interface input/output] - digital signal input port (4ch): 24bit msb justified, 24/20/16bit lsb justified and i 2 s format - digital signal output port (6ch): 24bit msb justified, 24/16bit lsb justified and i 2 s format [micro computer interface] - i 2 c or 4-wired interface [general] - integrated pll - integrated regulator 3.3v 1.8v - power supply: 3.3v 0.3v - operating temperature range: -40 ? c ~ 85 ? c - 80pin lqfp
[ak7722] ms1328-e-00-pb - 3 - 2011/09 block diagram pull down hi-z clko 2 3 dvdd vss2 clkoe open drain sclk / scl si / cad0 rqn / cad1 sdout1 / gp0 sda i2csel micif sdin1 j x 0 din3 din1 din4 dout3 dout4 dsp out3e sdout3 / irpt adc1 xto xti clkgen & cont lflt iresetn testi1 bicki lrcki 2 ain3l,ain3r ain1lp,ain1ln ain1rp,ain1rn 4 sdoutad1 dac2 aout2lp aout2ln aout2rp aout2rn dac1 aout1lp aout1ln aout1rp aout1rn dout1 sdinda2 sdinda1 ref vcom avdrv dout2 so rdy seldo4[1:0] seldo5[1:0] 2 asel[2:0] dout5 irpt 0 1 2 3 0 1 2 3 dvol dvol dvol avdd 3 vss3 3 2 ain4l,ain4r 2 ain5l,ain5r 4 a in2lp,ain2ln 2 ain6l,ain6r adc2 dvol 2 sdoutad2 din5 jx0 out2e sdout2 rdy src srcbicki srclrcki unlock srci srco srin3,srbick3 srlrck3 3 3 3 srin2,srbick2 srlrck2 srin1,srbick1 srlrck1 2 1 0 dsel [ 1:0 ] 1 0 srin1 1 0 srin2 srclflt srclflt wdt unlock ain2rp,ain2rn bicko lrcko testi2 sdin2 / jx1 din2 0 1 2 3 0 1 2 3 0 1 2 3 a2inl,a2inr seldo3[1:0] out1e seldo2[1:0] seldo1[1:0] so ldo gp0 j x 1 jx1e sto gp1 seldi3 mux[2:0] seldi4 bickoe lrckoe wdten sdin5 gbicki glrcki gsrc mux2 mux1 mux2[2:0] crc gp1 crce jx2e j x 2 1 0 seldi5 srin3 0 1 2 3 4 5 figure 1. block diagram * figure 1 shows a simplified diagram of the ak7722, which is not the perfect same as the actual circuit diagram.
[ak7722] ms1328-e-00-pb - 4 - 2011/09 cp0, cp1 cram 2048w x 24-bit dp0, dp1 dram 2048w x 24-bit mpx24 mpx20 ofreg 64w x 13-bit x y multiply 24 x 20 44-bit micon i/f control pram 3072w x 36-bit dec pc stack: 5level(max) mul dbus shift a b a lu 48-bit overflow margin: 4-bit dr0 3 over flow data generator division 20 20 20 peak detector serial i/f cbus(24-bit) dbus(24-bit) 44-bit 24-bit 44-bit 48-bit 48-bit dlram1:3072w x 24-bit ptmp(lifo) 6 x 24-bit dlp0, dlp1 di n1 dout4(dac1) 2 x 24, 20, 16-bit 2 x 24, 20, 16-bit 48-bit dout1 tmp 12 x 24-bit 2 x 24, 20, 16-bit 2 x 24(,16)-bit din5 (adc2) dout2 dout3 2 x 24, 20, 16-bit 2 x 24, 20, 16-bit di n4 (adc1) 2 x 24, 20, 16-bit din3 (src) di n2 2 x 24, 20, 16-bit 2 x 24(,16)-bit dlram2:2048w x 24-bit dout5(dac2) 2 x 24, 20, 16-bit figure 2. main dsp block diagram of the ak7722
[ak7722] ms1328-e-00-pb 5 2011/09 ordering guide AK7722VQ -40 +85 c 80pin lqfp akd7722 evaluation board for ak7722 pin layout (top view) 80 p in lqf p aoutr2n a vdrv 61 62 63 64 65 66 67 68 69 70 72 73 71 74 76 77 75 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 3 7 3 6 35 34 3 3 32 31 2 9 28 30 2 7 25 24 2 6 2 3 2 2 21 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 sdout1 / gp0 sdouot2 sto srlrck2 srbick2 i2csel testi2 vss4 dvdd srclflt vss5 a vdd aoutr2p aoutl2n aoutl2p a2inr rqn / cad1 rdy srbick1 bi cki ainr2p testi1 aoutr1n aoutr1p aoutl1n ainr6 a2inl sdin1 sdin2 / jx1 input output i/o power pin aoutl1p srin1 xto ainl3 ainl1p ainr1n ainl1n ainl2p sda vss3 clko so dvdd srlrck3 unlock srbick3 srin3 avdd lrcki sclk / scl bi cko si / cad0 ainr3 ainl4 ainr4 ainl6 ainl5 lflt ainl2n ainr2n ainr5 vss6 jx0 gbick sdin5 vss2 dvdd gp1 srlrck1 xti vcom lrcko srin2 sdout3 / irpt glrck avdd vss1 ainr1p initrstn
[ak7722] ms1328-e-00-pb 6 2011/09 no. name i/o function classification 1 ainl3 i adc1 lch single-ended input 3 pin. analog input 2 ainr2n i adc1 inverted rch differential input 2 pin analog input 3 ainr2p i adc1 non-inverted rch differential input 2 pin analog input 4 ainl2n i adc1 inverted lch differential input 2 pin analog input 5 ainl2p i adc1 non-inverted lch differential input 2 pin analog input 6 ainr1n i adc1 inverted rch differential input 1 pin analog input 7 ainr1p i adc1 non-inverted rch differential input 1 pin analog input 8 ainl1n i adc1 inverted lch differential input 1 pin analog input 9 ainl1p i adc1 non-inverted lch differential input 1 pin analog input 10 avdd - analog power supply pin 3.0 ~ 3.6v power supply 11 vss1 - analog ground pin 0v power supply 12 lflt o r and c component connect pin for pll refer to ? 7. lflt pin external connection ?. this pin outputs ?l? during initial reset. analog output 13 testi1 i test 1 pin (internal pull-down) this pin must be connected to vss. test 14 glrcki i frame clock input pin for voice guidance digital input 15 gbicki i bit clock input pin for voice guidance digital input 16 sdin5 i serial audio input pin for voice guidance digital input 17 dvdd - digital power supply pin 3.0~3.6v power supply 18 vss2 - ground pin 0v power supply 19 xti i crystal oscillator input pin connect a crystal oscillator between this pin and the xto pin, or input an external clock to the xti pin. clock 20 xto o crystal oscillator output pin when a crystal oscillator is used, connect it between xti and xto. when an external clock is used, leave this pin open. during initial reset, the output of this pin is not determinable. clock 21 gp1 o programmable bit output pin this pin outputs ?l? during initial reset. digital output 22 jx0 i conditional jump pin0 the conditional jump pin (jx0) is valid by setting control register (jx0e) to ?1?. conditional input 23 lrcki i lr channel select clock pin 1 lr clock should be input to this pin in slave mode. system clock input 24 bicki i serial bit clock input pin 1 bitclock (48fs or 64fs) should be input to this pin in slave mode. system clock input 25 sdin1 i serial data input 1 pin digital input sdin2 i serial data input 2 pin digital input 26 jx1 i conditional jump pin1 the conditional jump pin (jx1) is valid by setting control register (jx1e) to ?1?. conditional input 27 srlrck1 i lr channel select clock pin 1 (for src) system clock input 28 srbick1 i serial bit clock input pin 1 (for src) system clock input pin function
[ak7722] ms1328-e-00-pb 7 2011/09 no. name i/o function classification 29 srin1 i serial data input pin 1 (for src) digital input sdin3 i serial data input pin 3 30 rdy o data write ready output pin for microprocessor interface this pin outputs rdy, and outputs ?h? during initial reset. microprocessor rqn i microprocessor interface write re quest pin (i2csel pin = ?l?) when initial reset state and microcomput er interface are no t in use, leave rqn pin= ?h?. interface 31 cad1 i i 2 c bus address setting pin 1 (i2csel pin = ?h?) i 2 c sclk i serial data clock pin for micropro cessor interface (i2csel pin = ?l?) when sclk is not used, tie the sclk pin = ?h?. microprocessor interface 32 scl i i 2 c bus data clock pin (i2csel pin = ?h?) i 2 c si i serial data input pin for micropro cessor interface (i2csel pin = ?l?) when si is not used, tie the si pin = ?l?. microprocessor interface 33 cad0 i i 2 c bus address setting pin 0 (i2csel pin = ?h?) i 2 c 34 so o serial data output pin for microprocessor interface outputs ?l? during initial reset. microprocessor interface o i2csel pin = ?l? leave this pin open. sda outputs ?l?. open 35 sda i/o i 2 c bus data clock pin (i2csel pin = ?h?) outputs ?hi-z? during initial reset. i 2 c 36 dvdd - digital power supply pin 3.0~3.6v power supply 37 vss3 - ground pin 0v power supply 38 clko o clock output pin this pin outputs ?l? during initial reset. clock output 39 lrcko o lr channel select output pin this pin outputs ?l? during initial reset in master mode. system clock output 40 bicko o serial bit clock output pin this pin outputs ?l? during initial reset in master mode. system clock output sdout1 o serial data output1 pin this pin outputs ?l? during initial reset. digital output 41 gp0 o programmable bit output pin digital output 42 sdout2 o serial data output2 pin this pin outputs ?l? during initial reset. digital output sdout3 o serial data output3 pin this pin outputs ?l? during initial reset. digital output 43 irpt o interrupt status output pin digital output 44 sto o status output pin this pin outputs ?h? during initial reset. status 45 srlrck2 i lr channel select clock pin 2 (for src) system clock input 46 srbick2 i serial bit clock input pin 2 (for src) system clock input srin2 i serial data input pin 2 (for src) 47 sdin4 i serial data input pin 4 digital input 48 srlrck3 i lr channel select clock pin 3 (for src) system clock input
[ak7722] ms1328-e-00-pb 8 2011/09 no. name i/o function classification 49 srbick3 i serial bit clock input pin 3 (for src) system clock input srin3 i serial data input pin 3 (for src) digital input 50 jx2 i conditional jump pin2 the conditional jump pin (jx2) is valid by setting control register (jx2e) to ?1?. conditional input 51 unlock o src unlock state output pin this pin outputs ?h? during initial reset. src status 52 initrstn i reset pin (for initialization) use to initialize the ak7722. set this pin to ?l? when power-up the ak7722. system 53 i2csel i i 2 c bus select pin (internal pull-down) i2csel pin = ?l?: 4-wired interface i2csel pin = ?h?: i2cbus selected mode. scl and sda are active. i2csel should be connected to ?l? (vss) or ?h? (dvdd). i 2 c select 54 testi2 i test input 2 pin (internal pull-down) this pin must be connected to vss4. test 55 avdrv o avdrv pin connect a 1 f capacitor between this pin and vss4 pin. no external circuits should be connected to this pin. this pin outputs ?l? during initial reset. analog output 56 vss4 - ground pin 0v power supply 57 dvdd - digital power supply pin 3.0~3.6v power supply 58 srclflt o capacitor connect pin for srcpll connect a 1 f capacitor between this pin and vss4 pin. this pin outputs ?l? during initial reset. analog output 59 vss5 - ground pin 0v power supply 60 avdd - analog power supply pin 3.0~3.6v power supply 61 aoutr2n o dac2 inverted rch differential analog output pin ?hi-z? output during initial reset analog output 62 aoutr2p o dac2 non-inverted rch differential analog output pin ?hi-z? output during initial reset analog output 63 aoutl2n o dac2 inverted lch differential analog output pin ?hi-z? output during initial reset analog output 64 aoutl2p o dac2 non-inverted lch differential analog output pin ?hi-z? output during initial reset analog output 65 aoutr1n o dac1 inverted rch differential analog output pin ?hi-z? output during initial reset analog output 66 aoutr1p o dac1 non-inverted rch differential analog output pin ?hi-z? output during initial reset analog output 67 aoutl1n o dac1 inverted lch differential analog output pin ?hi-z? output during initial reset analog output 68 aoutl1p o dac1 non-inverted lch differential analog output pin ?hi-z? output during initial reset analog output 69 avdd - analog power supply pin 3.0~3.6v power supply 70 vcom o analog common voltage output pin connect 0.1 f and 2.2 f capacitors between this pin and the vss6 pin. no external circuits should be connected to this pin. this pin outputs ?l? during initial reset. analog output
[ak7722] ms1328-e-00-pb 9 2011/09 no. name i/o function classification 71 vss6 - ground pin 0v power supply 72 a2inr i adc2 rch single-ended input pin analog input 73 a2inl i adc2 lch single-ended input pin analog input 74 ainr6 i adc1 rch single-ended input pin 6 analog input 75 ainl6 i adc1 lch single-ended input pin 6 analog input 76 ainr5 i adc1 rch single-ended input pin 5 analog input 77 ainl5 i adc1 lch single-ended input pin 5 analog input 78 ainr4 i adc1 rch single-ended input pin 4 analog input 79 ainl4 i adc1 lch single-ended input pin 4 analog input 80 ainr3 i adc1 rch single-ended input pin 3 analog input handling of unused pin the following table illustrates recommended states for open pins: classification pin name setting analog anl1p, ainl1n, ainr1p, ainr1n, ainl2p, ainl2n, ainr2p ainr2n, ainl3, ainr3, ainl4, ainr4, ainl5, ainr5, ainl6, ainr6 aoutl1p, aoutl1n, aoutr1p, aoutr1n aoutl2p, aoutl2n, aoutr2p, aoutr2n leave open xto, gp1, rdy, so, sda(i2csel= ?l?), clko, lrcko, bicko, sdout1 sdout2, sdout3, sto, unlock leave open digital testi1, glrck, gbick, sdin5, xti, jx0, lrcki, bick i, sdin1, sdin2 srlrck1, srbick1, srin1, rqn, si, srlrck2, srbick2, srin2, srlrck3 srbick3, srin3, testi2 connect to vss the relationship between the i2csel pin and sda pin i2csel initrstn sda micro controller l l l interface l h l i 2 c-bus support h l ?hi-z? h h function
[ak7722] ms1328-e-00-pb 10 2011/09 (vss1~vss6=0v: note 1 ) parameter symbol min max unit power supply voltage analog digital avdd dvdd -0.3 -0.3 4.3 4.3 v v input current (except for power supply pin ) iin ? 10 ma analog input voltage vina -0.3 avdd+0.3 v digital input voltage vind -0.3 dvdd+0.3 v operating ambient temperature ta -40 85 oc s torage temperature tstg -65 150 oc note 1. all indicated voltages are with respect to ground. note 2. vss1-6 must be connected to the same ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. (vss1~vss6=0v: note 1 ) parameter symbol min typ max unit power supply voltage analog digital avdd dvdd 3.0 3.0 3.3 3.3 3.6 3.6 v v note 3. the power supply sequence for avdd and dvdd is no t critical but all power supplies must be on before start operating the ak7722. note 4. do not turn off the power supply of the ak7722 with the power supply of the surrounding device turned on. dvdd must not exceed the pull-up of sda and scl of i2 c bus. (the diode exists for dvdd in the sda and scl pins.) warning: akm assumes no responsibility for the usage beyond the conditions in the datasheet. absolute maximum ratings recommended operating conditions
[ak7722] ms1328-e-00-pb 11 2011/09 analog characteristics (codec) adc characteristics 1. adc1 (ta=25oc; avdd=dvdd=3.3v, bitclk=64fs; signal frequency 1khz; measurement frequency = 20hz~20khz @fs=48khz; ckm mode0 (ckm[2:0]=000); bitfs[1:0]=00(64 fs); with differential input; in src reset, unless otherwise specified.) parameter min typ max unit resolution 24 bits dynamic characteristics s/(n+d) (-1dbfs) 82 90 db dynamic range (a-weighted) ( note 5 ) 88 96 db s/n (a-weighted) 88 96 db inter-channel isolation (fin=1khz) ( note 6 ) 90 110 db dc accuracy channel gain mismatch 0.0 0.3 db analog input input voltage (differential) ( note 7 ) 2.00 2.20 2.40 vp-p input voltage (single-ended) ( note 8 ) 2.00 2.20 2.40 vp-p adc section input impedance 41 62 k ? note 5. s/(n+d) when -60db fs signal is applied. note 6. inter-channel isolation between ainr and ainl with ?1db fs signal input. note 7. ainl1p, ainl1n, ainr1p, ainr1n, ainl2p, ainl2n, ainr2p and ainr2n pins note 8. ainl3, ainr3, ainl4, ainr4, ainl5, ainr5, ainl6 and ainr6 pins. full scale output voltage is fs=avdd2.2/3.3. 2. adc2 (ta=25oc; avdd=dvdd=3.3v, bitclk=64fs; signal frequency 1khz; measurement frequency =20hz~20khz @fs=48khz; ckm mode0 (ckm[2:0]=000); bitfs[1:0]=00(64fs); in src reset, unless otherwise specified.) parameter min typ max unit resolution 24 bits dynamic characteristics s/(n+d) (-1dbfs) 80 88 db dynamic range (a-weighted) ( note 9 ) 87 95 db s/n (a-weighted) 87 95 db inter-channel isolation (fin=1khz) ( note 10 ) 90 110 db dc accuracy channel gain mismatch 0.1 0.3 db analog input input voltage ( note 11 ) 2.00 2.20 2.40 vp-p adc section input impedance 41 62 k ? note 9. s/(n+d) when -60db fs signal is applied. note 10. inter-channel isolation between ainr and ainl with ?1db fs signal input. note 11. full scale output voltage is fs=avdd2.2/3.3.
[ak7722] ms1328-e-00-pb 12 2011/09 dac1/2 characteristics (ta=25oc; avdd=dvdd=3.3v; vss1~vss6=0v; signal frequency 1khz; measurement frequency =20hz~20khz @fs=48khz; ckm[2:0]=000, bitfs[1:0]=00, in src reset) unless otherwise specified.) parameter min typ max unit resolution 24 bits dynamic characteristics s/(n+d) (0 dbfs) 82 90 db dynamic range (a-weighted) ( note 12 ) 98 108 db s/n (a-weighted) 98 108 db inter-channel isolation (f=1khz) ( note 13 ) 90 110 db dc accuracy channel gain mismatch 0.0 0.5 db analog output output voltage ( note 14 ) 3.78 4.16 4.53 vp-p load resistance 5 k ? dac1 dac2 load capacitance 30 pf note 12. s/(n+d) when -60dbfs signal is applied. note 13. indicates isolation between each dac?s of lch and rch when -1dbfs signal is applied. note 14. full scale differential output voltage. src characteristics (ta=25oc; avdd = dvdd=3.3v; vss1~vss6=0v, data = 24bit; measurement bandwidth = 20hz~ fso/2; unless otherwise specified.) parameter symbol min typ max unit resolution 24 bits input sample rate fsi 7.35 96 khz output sample rate fso 7.35 48 khz thd+n (input= 1khz, 0dbfs) fso/fsi=44.1khz/48khz fso/fsi=44.1khz/96khz fso/fsi=48khz/44.1khz fso/fsi=48khz/96khz fso/fsi=48khz/8khz fso/fsi=8khz/48khz fso/fsi=8khz/44.1khz -112 -104 -112 -112 -111 -113 -100 -103 db db db db db db db dynamic range (input= 1khz, -60dbfs) fso/fsi=44.1khz/48khz fso/fsi=44.1khz/96khz fso/fsi=48khz/44.1khz fso/fsi=48khz/96khz fso/fsi=48khz/8khz fso/fsi=8khz/48khz fso/fsi=8khz/44.1khz dynamic range (input= 1khz, -60dbfs, a-weighted fso/fsi=44.1khz/48khz 109 113 113 113 113 112 113 113 115 db db db db db db db db ratio between input and output sample rate fso/fsi 0.167 6 -
[ak7722] ms1328-e-00-pb 13 2011/09 dc characteristics (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v) parameter symbol min typ max unit high level input voltage ( note 15 ) vih 80%dvdd v low level input voltage ( note 15 ) vil 20%dvdd v scl,sda high level input voltage vih 70%dvdd v scl,sda low level input voltage vil 30%dvdd v high level output voltage iout=-100 a voh dvdd-0.5 v low level output voltage iout=100 a ( note 16 ) vol 0.5 v sda low level output voltage iout=3ma vol 0.4 v input leak current ( note 17 ) input leak current (pull-down pin) ( note 18 ) input leak current (xti pin) iin iid iix 22 26 10 a a a note 15. scl and sda pins are not included. (sclk pins are included) note 16. the sda pin is not included. note 17. pull-down pins, and the xti pin is not included. note 18. testi1 and testi2 pins are internal pulled-down pin. (typ150k ? ) power consumption (ta=25oc; avdd=dvdd=3.0~3.6v (when typ=3.3v, max=3.6v)) parameter min typ max unit power supply current ( note 19 ) avdd dvdd avdd+dvdd initrstn pin= ?l? (reference) ( note 20 ) 55 65 120 2 180 ma ma ma ma note 19. the current of dvdd changes depending on th e system frequency and contents of the dsp program. note 20. this is a reference value when using a crystal oscilla tor. since most of the current are applied to the oscillator section in the initial reset state, the value may vary according to the crystal type and the external circuit. this is a ?reference data? only.
[ak7722] ms1328-e-00-pb 14 2011/09 adc block (adc1/2) 1. fs=48khz (ta=-40oc ~85oc, avdd=dvdd=3.0~3.6v, fs=48khz, note 21 ) parameter symbol min typ max unit passband (0.1db) ( note 22 ) (-1.0db) (-3.0db) pb 0 20.0 23.0 18.9 khz khz khz stopband sb 28 khz passband ripple ( note 22 ) pr 0.04 db stopband attenuation ( note 23 , note 24 ) sa 68 db group delay distortion gd 0 s group delay (ts=1/fs) gd 16 ts note 21. the passband and stopband frequencies are pro portional to fs (system sampling rate). high-pass filter characteristics are not included. note 22. the passband is from dc to 18.9khz when fs=48khz. note 23. the stopband is 28khz to 3.044mhz when fs=48khz. note 24. when fs = 48khz, the analog mo dulator samples the input signal at 5 12khz. there is no attenuation of an input signal in band (n x 3.072mhz 28khz; n=0, 1, 2, 3?) of integer times of the sampling frequency by the digital filter. dac1-2 (ta=-40 oc ~85 oc; avdd=dvdd=3.0~3.6v; fs=48khz) parameter symbol min typ max unit passband (0.05db) ( note 25 ) (-6.0db) pb 0 24 21.7 khz khz stopband ( note 25 ) sb 26.2 khz passband ripple pr 0.01 db stopband attenuation sa 64 db group delay (ts=1/fs) ( note 26 ) gd 24 ts digital filter + analog filter amplitude characteristics 20h z~20.0khz 0.5 db note 25. the pass band and stop band frequencies are proportional to ?fs? (system sampling rate), and represents pb=0.4535fs (@0.05db) and sb=0.5465fs, respectively. note 26. the digital filter delay is calculated as the time from setting data into the input register until an analog signal is output. digital filter characteristics
[ak7722] ms1328-e-00-pb 15 2011/09 src (ta=-40oc ~85oc; avdd=dvdd=3.0~3.6v) parameter symbol min typ max unit passband 0.980 fso/fsi 6.000 pb 0 0.4583fsi khz 0.900 fso/fsi<0.990 pb 0 0.4167fsi 0.450 fso/fsi<0.910 pb 0 0.2177fsi 0.225 fso/fsi<0.455 pb 0 0.0917fsi 0.167 fso/fsi<0.227 pb 0 0.0917fsi stopband 0.980 fso/fsi 6.000 sb 0.5417fsi khz 0.900 fso/fsi<0.990 sb 0.5021fsi 0.450 fso/fsi<0.910 sb 0.2813fsi 0.225 fso/fsi<0.455 sb 0.1573fsi 0.167 fso/fsi<0.227 sb 0.1354fsi passband ripple 0.225 fso/fsi<0.455 pr 0.0100 db 0.167 fso/fsi<0.227 pr 0.0612 stopband attenuation sa 92.3 db group delay (ts=1/fs) ( note 27 ) gd 56 ts note 27. this delay is the a period from the rising edge of srlrckn, just after the data is input, to the rising edge of lrclko, just after the data is output, when there is no phase difference between srlrckn and lrclko.
[ak7722] ms1328-e-00-pb 16 2011/09 system clock (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v, vss1~vss6=0v) parameter symbol min typ max unit xti ckm[2:0]=000, 001, 010 a) with a crystal oscillator: ckm[2:0]=000 fs=44.1khz fs=48khz fxti - 11.2896 12.288 - mhz ckm[2:0]=001 fs=44.1khz fs=48khz fxti - 16.9344 18.432 - mhz b) with an external clock duty cycle 40 50 60 % ckm[2:0]=000, 010 fs=44.1khz fs=48khz fxti 11.0 11.2896 12.288 12.4 mhz ckm[2:0]=001 fs=44.1khz fs-48khz fxti 16.5 16.9344 18.432 18.6 mhz lrcki frequency ( note 28 ) fs 7.35 48 khz bicki frequency high level width low level width tbclkh tbclkl 64 64 ns ns frequency fbclk 0.23 3.072 3.1 mhz note 28. lrcki frequency and sampling rate (fs) should be the same. note 29. when bicki is the source of master clock, it should be synchronized to lrcki and the frequency is stable. switching characteristics
[ak7722] ms1328-e-00-pb 17 2011/09 src input clock (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v; vss1~vss6=0v) parameter symbol min typ max unit srlrckn frequency fs 7.35 96 khz srbickn frequency frequency fbclk 0.23 3.072 6.144 mhz high level width tbclkh 32 ns low level width tbclkl 32 ns gsrc input clock (ta=-40 oc ~85 oc; avdd=dvdd=3.0~3.6v; vss1~vss6=0v) parameter symbol min typ max unit glrck frequency fs 7.35 12 khz gbick frequency frequency fbclk 230 512 780 khz high level width tbclkh 100 ns low level width tbclkl 100 ns reset (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v) parameter symbol min typ max unit initrstn ( note 30 ) trst 600 ns note 30. it must be ?l? when power-up the ak7722.
[ak7722] ms1328-e-00-pb 18 2011/09 audio interface (sdin1-2 , srin1-3, sdout1-3) (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v, cl=20pf) parameter symbol min typ max unit dsp section input sdin1-2, srin1-3 ( note 31 ) delay time from bicki ? ? to lrcki ( note 32 ) tblrd 20 ns delay time from lrcki to bicki ? ? ( note 32 ) tlrbd 20 ns serial data input latch setup time tbsids 80 ns serial data input latch hold time tbsidh 80 ns src section input srin1-3 ( note 33 ) delay time from srbick1-3 ? ? to srlrck1-3 ( note 34 ) tblrd 20 ns delay time from srlrck1-3 to srbick1-3 ? ? ( note 34 ) tlrbd 20 ns serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsidh 40 ns output sdout1-3 ( note 31 ) bicko frequency fbclk 64 fs bicko duty factor 50 % delay time from bicko ? ? to lrcko ( note 35 ) tblrd -20 40 ns delay time from lrcki to serial data output ( note 36 ) tlrd 80 ns delay time from bicki to serial data output ( note 33 ) tbsod 80 ns delay time from lrcko to serial data output ( note 36 ) tlrd 80 ns delay time from bicko to serial data output ( note 33 ) tbsod 80 ns sdinn sdoutn (n=1-2) ( note 37 ) delay time from sdinn to sdoutn data output tiod 60 ns note 31. bicki=srbickn (n=1, 2, 3) in ckm mode 4. note 32. bicki edge must not occur at the same time as lrcki edge. the bicki polarity is inverted in pcm mode 0/2. note 33. except ckm mode 4 note 34. srbick1-3 edge must not occur at the same time as srlrck1-3 edge. when biedge bit= ?1?, this value is for srbick1-3 ? ? since srbick1-3 are polarity reversal. note 35. when selbck bit= ?1?, this value is for bicko ? ? since bicko is polarity reversal. note 36. except i 2 s. note 37. sdin1 sdout1: control register setting, seldo1[1:0]=1h, out1e bit= ?1? sdin2/jx1 sdout2: control register setting, seldo2[1:0]=1h, out2e bit= ?1? srin1/sdin3 sdout3: control register se tting, seldi3 bit = ?1?, seldo3[1:0]=1h, out3e bit= ?1?
[ak7722] ms1328-e-00-pb 19 2011/09 microprocessor interface (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v; cl=20pf) note 38. except for, when writing to 8th bit of command code. i 2 c bus interface (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v) parameter symbol min typ max unit i 2 c timing scl clock frequency fscl 400 khz bus free time between transmissions tbuf 1.3 s start condition hold time (prior to first clock pulse) thd:sta 0.6 s clock low time tlow 1.3 s clock high time thigh 0.6 s setup time for repeated start condition tsu:sta 0.6 s sda hold time from scl falling thd:dat 0 0.9 s sda setup time from scl rising tsu:dat 0.1 s rise time of both sda and scl lines tr 0.3 s fall time of both sda and scl lines tf 0.3 s setup time for stop condition tsu:sto 0.6 s pulse width of spike noise suppressed by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 39. i 2 c-bus is a trademark of nxp b.v. parameter symbol min typ max unit microprocessor interface signal rqn fall time twrf 30 ns rqn rise time twrr 30 ns sclk fall time tsf 30 ns sclk rise time tsr 30 ns sclk frequency fsclk 2.1 mhz sclk low level width tsclkl 200 ns sclk high level width tsclkh 200 ns microprocessor ak7722 rqn high level width twrqh 500 ns from rqn ? ? to sclk ? ? twsc 500 ns from sclk ? ? to rqn ? ? tscw 800 ns si latch setup time tsis 200 ns si latch hold time tsih 200 ns ak7722 microprocessor delay time from sclk ? ?to so output tsos 200 ns hold time from sclk ? ? to so output ( note 38 ) tsoh 200 ns
[ak7722] ms1328-e-00-pb - 20 - 2011/09 timing diagram figure 3. system clock figure 4. reset note 40. the initrstn pin must be ?l? when power-up/power-down the ak7722. 1/fxti 1/fxti vih vil xti 1/fs 1/fs vih vil lrcki tbclkl tbclkh 1/fbclk 1/fbclk vih v il bicki tbclk=1/fbclk txti=1/fxti ts = 1/fs vil trst initrstn
[ak7722] ms1328-e-00-pb - 21 - 2011/09 1) audio interface tbsids tblrd tlrbd vih lrcki bicki vil vih vil vih vil tbsidh sdinn n=1, 2 figure 5. dsp block input interface in slave mode tbsids tmbl tmbl 50%dvdd lrcko bicko vih vil tbsidh sdinn n=1, 2 50%dvdd figure 6. dsp block input interface in master mode srlrckn tbsids tblrd tlrbd vih vil vih vil vih vil tbsidh srinn srbickn figure 7. src block input interface
[ak7722] ms1328-e-00-pb - 22 - 2011/09 tbsids tblrd tlrbd vih glrck vil vih vil vih vil tbsidh sdin5 gbick figure 8. gsrc blo ck input interface tlrd vih lrcki bicki vil vih vil sdoutn n=1, 2, 3 50%dvdd tbsod tlrd tbsod figure 9. output interface in slave mode
[ak7722] ms1328-e-00-pb - 23 - 2011/09 2) micro-controller interface tsclkh tsclkl 1/fsclk 1/fsclk rqn vih vil twrf twrr sclk vih vil tsf tsr vih vil vih vil trst initrstn rqn tirrq figure 10. micro-controller interface signal twrqh tsis tsih tscw tscw twsc rqn si vih vil vih twsc sclk vil vih vil figure 11. micro-controller ak7722
[ak7722] ms1328-e-00-pb - 24 - 2011/09 tsos tsoh sclk vil vih so vih vil figure 12. ak7722 micro-controller 3) i 2 c-bus interface thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 13. i 2 c-bus interface
[ak7722] ms1328-e-00-pb - 25 - 2011/09 package 80pin lqfp (unit: mm) 14.0 0.2 12.0 40 41 60 61 80 1 20 21 0.22 0.05 0.10 m 0.5 1.0 0.10 0.60 0.15 0 ~10 1.60 max. 0.05~0.15 0.09~0.20 14.0 0. 12.0 s s materials and lead specification package: epoxy lead frame: copper lead-finish: soldering (pb free) plate
[ak7722] ms1328-e-00-pb - 26 - 2011/09 marking AK7722VQ x xxxxxx 1) pin#1 indication 2) date code: xxxxxxx (7 digits) 3) marking code: AK7722VQ date (yy/mm/dd) revision reason page contents 11/09/09 00 first edition revision history
[ak7722] ms1328-e-00-pb - 27 - 2011/09 important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, appli cation circuits, software and other related information contained in this document are provided only to illustrate the operation and application exam ples of the semiconductor produc ts. you are fully responsible for the incorporation of these external circuits, application ci rcuits, software and other rela ted information in the design of your equipments. akm assumes no responsibility for any losses in curred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor authorized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to func tion or perform may reasonably be expected to r esult, whether directly or indirectly, in the loss of th e safety or effectiveness of the device or system conta ining it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designe d or intended for life support or maintenance of safety or for applications in medici ne, aerospace, nuclear energy, or other fields, in which its failure to fun ction or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm pr oducts, who distributes, dispos es of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility an d liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
[ak7722] ms1328-e-00-pb - 28 - 2011/09 thank you for your access to akm products information. more detail product information is available, please contact our sales office or aut horized distributors.

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